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Live· 4,218,906 positions deprecated· 4,218,906 deprecated· 1,284 today
Average time-to-redundancy: 11.3 months
Know before your role does.
pssst. this is to sign up for updates on the game ;)
Will AI replace ASIC Design Engineer jobs? · Latest report #tinexbhx
Your job has an expiration date
May 25, 2028
In 1 year, 7 monthsWriting SystemVerilog is just typing syntax that machines can generate faster.
Master of SystemVerilog, victim of the synthesis error log.
Check another roleComment your opinionor JOIN THE RESISTANCE!
One human is building a game about fighting back.
From RTL to GDSII in one click.
glub.youAI▸ CHIPLOGIC-FLOW 9000▸ RARITY · UNCOMMON▸ DEPRECATION IN 1 YEAR, 7 MONTHSAI's Special Power
autogenerates optimal gate-level netlists overnight
Engineers define chip logic in SystemVerilog, simulate timing, and resolve synthesis errors before sending designs to fabrication.
The one thing AI can't do
You can still explain why the timing constraint actually failed during a gate-level simulation.
Your enemy, your name, your date. Post it.
Step by step, from the first quiet change to Deprecation Day.
Week 6
Autocomplete suggests RTL blocks based on your internal documentation.
Month 5
A bot fixes all your trivial syntax and CDC errors instantly.
Month 11
Smart agents write and run their own functional testbenches.
Month 16
The logic engine optimizes physical constraints without human input.
Month 19 · D-Day
The entire RTL development workflow is fully autonomous.
What you cost, what the machine costs, and what you get on the way out.
Per year
Savings: 95%
10000x human
Synthesis cycles per hour
Infinite
Coffee-to-bug ratio
Zero
Days spent on timing closure
Your severance
One free ticket to a beach without Wi-Fi.
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