Retrieving the file
Live· 4,218,906 positions deprecated· 4,218,906 deprecated· 1,284 today
Average time-to-redundancy: 11.3 months
Know before your role does.
pssst. this is to sign up for updates on the game ;)
Will AI replace Digital IC Design Engineer jobs? · Latest report #njuyxfbd
Your job has an expiration date
May 24, 2028
In 1 year, 7 monthsYour Verilog is just a slow, clumsy way of describing circuit logic.
HDL architect (mostly SystemVerilog, perpetually fighting synthesis)
Check another roleComment your opinionor JOIN THE RESISTANCE!
One human is building a game about fighting back.
Turning high-level ideas into physical wafers instantly.
help!youAI▸ SILICONARCHITECT AI V9▸ RARITY · UNCOMMON▸ DEPRECATION IN 1 YEAR, 7 MONTHSAI's Special Power
optimizes gate-level power consumption in seconds
You write RTL code to define chip logic and run simulations. Then you spend weeks chasing timing violations.
The one thing AI can't do
You are uniquely capable of arguing why the physical constraints were ignored by management.
Your enemy, your name, your date. Post it.
Step by step, from the first quiet change to Deprecation Day.
Day 10
AI models start catching your syntax errors before you even compile.
Month 5
Smart software replaces manual script tuning for area and power targets.
Month 10
Generative agents write all testbenches and cover every single edge case.
Month 15
Self-routing algorithms fix all timing violations without your messy human intervention.
Month 19 · D-Day
The silicon tape-out process finishes without a single human finger involved.
What you cost, what the machine costs, and what you get on the way out.
Per year
Savings: 96.9%
4 liters
Coffee consumption per bug
22 percent
Average simulation failure rate
60 percent
Time spent in meetings
Your severance
One free USB-C hub and a PDF of regret.
Discussion
