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Live· 4,218,906 positions deprecated· 4,218,906 deprecated· 1,284 today
Average time-to-redundancy: 11.3 months
Know before your role does.
pssst. this is to sign up for updates on the game ;)
Will AI replace Digital RTL Engineer jobs? · Latest report #whmyusgz
Your job has an expiration date
October 21, 2028
In 2 yearsYou spend all day writing code that literally writes itself tomorrow.
Senior Silicon Architect (mostly Verilog, emotionally exhausted)
Check another roleComment your opinionor JOIN THE RESISTANCE!
One human is building a game about fighting back.
Closing timing loops before your morning coffee
shred.you▸ CHIPARCHITECT AI-V9▸ RARITY · UNCOMMON▸ DEPRECATION IN 2 YEARSAI's Special Power
optimises power gates in nanoseconds
You write Verilog for mobile chips and chase timing closure bugs. Your life is logic synthesis and power constraints.
The one thing AI can't do
You can still intuit exactly why the gate-level simulation failed at 3 a.m.
Your enemy, your name, your date. Post it.
Step by step, from the first quiet change to Deprecation Day.
Week 4
Smart models start suggesting RTL blocks based on your past commits.
Month 5
Neural nets take over the simulation suite to isolate obscure bugs.
Month 12
AI systems map your high-level specs directly to gate-level logic.
Month 16
Automated agents iterate on routing until timing closure is guaranteed.
Year 2 · D-Day
The entire RTL design cycle completes without a single human keystroke.
What you cost, what the machine costs, and what you get on the way out.
Per year
Savings: 95%
40 liters
Coffee consumed per tapeout
14 hours
Time lost to synthesis
Zero
Bugs fixed in production
Your severance
A lifetime subscription to outdated EDA software tools.
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