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Live· 4,218,906 positions deprecated· 4,218,906 deprecated· 1,284 today
Average time-to-redundancy: 11.3 months
Know before your role does.
pssst. this is to sign up for updates on the game ;)
Will AI replace RTL Silicon Design Engineer jobs? · Latest report #rksfkz48
Your job has an expiration date
May 24, 2028
In 1 year, 7 monthsWriting millions of lines of hardware code to describe a physical box.
Logic gate whisperer with a terminal case of timing-anxiety.
Check another roleComment your opinionor JOIN THE RESISTANCE!
One human is building a game about fighting back.
From RTL to GDSII without the humans.
squeeze.youAI▸ CHIPARCHITECT AI V4.2▸ RARITY · UNCOMMON▸ DEPRECATION IN 1 YEAR, 7 MONTHSAI's Special Power
optimizes gate paths while you sleep
You translate system requirements into synthesizable Verilog or VHDL. Then you verify the logic timing constraints endlessly.
The one thing AI can't do
You can sense the phantom physical gate delay in a simulation gone horribly wrong.
Your enemy, your name, your date. Post it.
Step by step, from the first quiet change to Deprecation Day.
Week 4
Language models start predicting your Verilog modules before you type them.
Month 5
AI agents find every logic error before you even hit save.
Month 10
Neural solvers generate testbenches that cover every possible edge case.
Month 15
Machines tune synthesis parameters to hit performance goals automatically.
Month 19 · D-Day
Your code is obsolete as AI generates hardware directly from specs.
What you cost, what the machine costs, and what you get on the way out.
Per year
Savings: 96.9%
12 cups
Coffee per timing closure
4.2
Logic bugs per week
89%
Synthesis time wasted
Your severance
A lifetime subscription to outdated EDA software tools.
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