Retrieving the file
Live· 4,218,906 positions deprecated· 4,218,906 deprecated· 1,284 today
Average time-to-redundancy: 11.3 months
Know before your role does.
pssst. this is to sign up for updates on the game ;)
Will AI replace Senior Technical Leader jobs? · Latest report #ybmty7yx
Your job has an expiration date
April 14, 2028
In 1 year, 6 monthsYou spend all day optimizing logic gates only to be replaced by them.
Senior FPGA Architect (mostly Verilog, occasionally weeping)
Check another roleComment your opinionor JOIN THE RESISTANCE!
One human is building a game about fighting back.
Designing your next circuit board in microseconds
splat.you▸ LOGICGATE-OPTIMIZER 9000▸ RARITY · UNCOMMON▸ DEPRECATION IN 1 YEAR, 6 MONTHSAI's Special Power
compiles entire hardware projects in seconds
You manage hardware requirements and oversee HDL code development for FPGA-based government systems. You solve synthesis and routing errors.
The one thing AI can't do
You can still explain why the hardware timing constraints failed under extreme environmental load.
Your enemy, your name, your date. Post it.
Step by step, from the first quiet change to Deprecation Day.
Week 4
AI starts flagging inefficient Verilog logic before you even commit.
Month 4
Smart agents begin fine-tuning timing constraints to save you hours.
Month 8
A neural model writes the hardware specifications from government PDFs directly.
Month 13
Virtual environments run every possible edge case without human input.
Month 18 · D-Day
The system designs, routes, and simulates its own hardware upgrades forever.
What you cost, what the machine costs, and what you get on the way out.
Per year
Savings: 97.5%
4 minutes
Average synthesis runtime
8 cups
Required coffee intakes
too many
Logic errors detected
Your severance
One lifetime supply of lead-free solder paste.
Discussion
