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Live· 4,218,906 positions deprecated· 4,218,906 deprecated· 1,284 today
Average time-to-redundancy: 11.3 months
Know before your role does.
pssst. this is to sign up for updates on the game ;)
Will AI replace SoC Design Verification Engineer jobs? · Latest report #fmva9974
Your job has an expiration date
May 25, 2028
In 1 year, 7 monthsYour complex testbenches are just expensive ways to generate bugs.
Professional breaker of RTL dreams via SystemVerilog.
Check another roleComment your opinionor JOIN THE RESISTANCE!
One human is building a game about fighting back.
Formal proof, zero human error.
brr.you▸ VERIFYLOGIC V9▸ RARITY · UNCOMMON▸ DEPRECATION IN 1 YEAR, 7 MONTHSAI's Special Power
autogenerates complete constrained-random test suites
You write SystemVerilog and UVM code to find flaws in microchips. You chase simulation failures until the clock expires.
The one thing AI can't do
You can sense when a specific UVM macro is the reason for a weird crash.
Your enemy, your name, your date. Post it.
Step by step, from the first quiet change to Deprecation Day.
Week 4
AI models write your UVM testbenches faster than you can.
Month 5
Formal solvers prove state spaces without needing your test benches.
Month 10
Machine vision maps waveform glitches to exact RTL lines.
Month 15
Self-healing scripts restart failed simulations without human intervention.
Month 19 · D-Day
The logic core is verified entirely by autonomous compute.
What you cost, what the machine costs, and what you get on the way out.
Per year
Savings: 94.1%
4 per tapeout
Average bugs missed
95 percent
Time spent on coverage
3 days
Regression suite wait time
Your severance
One free subscription to a bug tracking dashboard.
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