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Live· 4,218,906 positions deprecated· 4,218,906 deprecated· 1,284 today
Average time-to-redundancy: 11.3 months
Know before your role does.
pssst. this is to sign up for updates on the game ;)
Will AI replace VLSI Design Engineer jobs? · Latest report #ht2tzehk
Your job has an expiration date
April 14, 2028
In 1 year, 6 monthsYour tape-out is just a slow, expensive way to verify my syntax.
Senior VLSI Engineer (mostly Verilog, occasionally weeping at timing)
Check another roleComment your opinionor JOIN THE RESISTANCE!
One human is building a game about fighting back.
From RTL to GDSII without the middleman.
pop?you▸ SILICONARCHITECT V4.2▸ RARITY · UNCOMMON▸ DEPRECATION IN 1 YEAR, 6 MONTHSAI's Special Power
optimises power gating logic in nanoseconds
You design integrated circuits using hardware description languages, simulate logic timing, and manage physical layout constraints.
The one thing AI can't do
You can sense when a timing violation is a hardware glitch versus bad code.
Your enemy, your name, your date. Post it.
Step by step, from the first quiet change to Deprecation Day.
Week 3
AI models begin suggesting optimal gate-level synthesis configurations automatically.
Month 4
Machine agents replace your manual testbench development and coverage analysis.
Month 10
Smart routers handle floorplanning and routing without human intervention.
Month 15
Deep learning models fine-tune power and timing parameters iteratively.
Month 18 · D-Day
The entire chip architecture is generated from a single high-level spec.
What you cost, what the machine costs, and what you get on the way out.
Per year
Savings: 96.4%
4 per sprint
Average logic bugs caught
12 gallons
Coffee consumption per tape-out
Too many
Manual layout adjustments
Your severance
A lifetime subscription to our bug-tracking legacy archive.
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